1. Field of the Invention
The present invention relates to a polishing fluid used in a step of manufacturing a semiconductor integrated circuit, and a polishing method using the same.
2. Description of the Related Art
Recently, there has been demand for an increase in density and an increase in integration by means of miniaturizing and laminating wirings in pursuit of size reduction and increased speed in the development of semiconductor devices represented by semiconductor integrated circuits (hereinafter, sometimes, referred to as “LSI”). A variety of techniques, such as chemical mechanical polishing (hereinafter, sometimes referred to as “CMP”), have been used as techniques for this pursuit. The CMP is an essential technique when carrying out the surface flattening of a film workpiece, such as an interlayer insulation film, plug formation, formation of embedded metal wirings, and the like, and the CMP carries out the flattening and the like of substrates.
In an ordinary method of the CMP, a polishing pad is attached to a round polishing platen, the surface of the polishing pad is soaked with a polishing fluid, the surface (surface to be polished) of a substrate (wafer) is pressed to the pad, and both the polishing platen and the substrate are rotated in a state in which a predetermined pressure (polishing pressure) is applied from the rear surface of the substrate, thereby flattening the surface of the substrate by mechanical friction generated.
In recent years, the CMP has been applied to each step in the manufacture of semiconductors, and an example of an aspect thereof includes an application to the gate forming step in the manufacture of transistors.
In this case, gates mainly made of modified polysilicon obtained by injecting impurities, such as B, to polysilicon have been manufactured for transistors in the related art, but ongoing studies are being carried out regarding the application of high-dielectric constant gate insulation films (high-k films) and metal gate electrodes, instead of polysilicon in the related art, to transistors of 45 nm-generation or later to satisfy both the reduction of power consumption during standby and high-current operation capabilities. Several methods have been suggested as technologies in which the above is applied. For example, a method in which a dummy gate insulation film and a dummy gate electrode are formed, a source drain diffusion layer is formed by injecting impurities to a polycrystalline silicon film in a self-aligning manner, the dummy gate insulation film and the dummy gate electrode are removed, and a high-dielectric constant gate insulation film and a metal gate electrode are then formed is suggested (for example, refer to JP2007-12922A).
In addition, several techniques have been suggested regarding the method of forming a metal gate electrode. A fully silicided gate (hereinafter, referred to as “FUSI gate”) is one of the candidates thereof. The FUSI gate is formed by siliciding a gate electrode formed of polysilicon, similarly to the CMOS process in the related art, but the entire gate electrode is silicided in the FUSI while only the top portion of the gate electrode was silicided in the related art. The FUSI has a large merit in building processes in comparison to the method in which a metal gate electrode is formed by the damascene process since the know how of the CMOS process in the related art becomes useful.
In recent years, it has been suggested to selectively perform the CMP on polysilicon and the like and the second and the third materials that cover the periphery of the polysilicon when a gate is formed using the above polysilicon or modified polysilicon (hereinafter referred to simply and collectively as “polysilicon and the like”) (for example, refer to JP-H06-124932A (JP1994-124932A) and JP2009-540575A). However, when a polishing workpiece including polysilicon and the like is polished by the CMP using a well-known polishing fluid in the related art, there is a problem in that polysilicon and the like which the manufacturer wants to remain as a gate material are excessively polished, which may, furthermore, cause performance degradation or the like of the obtained LSI.
For the purpose of solving the problems of the performance degradation and the like of an LSI, JP2009-290126A discloses a polishing fluid that is used for the chemical mechanical polishing of polishing workpieces which are configured to have at least a first layer including polysilicon or modified polysilicon, and a second layer including at least one selected from a group consisting of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, and silicon oxynitride; contains colloidal silica particles, an organic acid, and an anionic surfactant; has a pH of 1.5 to 7.0; and can selectively polish the second layer with respect to the first layer.